1. Technical Field
The present invention relates to a semiconductor device and a method of manufacturing the same, and in particular to a semiconductor device having a multilayer interconnection structure and a method of manufacturing the same.
2. Related Art
Devices and interconnect lines in semiconductor integrated circuits have been scaled down for the purpose of improving the characteristics and reducing the cost per function. The electrical specifications of devices such as transistors are improved by scaling (down) and other several solutions. On the other hand, because of the scaling (down) of interconnect lines, a remarkable increase occurs in the line resistance and the inter-line capacitance. The delay constant of signal propagation along interconnect line is represented by the product of the line resistance and the inter-line capacitance. In recent semiconductor integrated circuits, the delay of signal propagation along interconnect lines has become a bottleneck limiting the circuit operation speed because of the increase in the line resistance and the inter-line capacitance due to the scaling down of interconnect lines. Under such situation, a low dielectric constant material having a smaller relative dielectric constant than a conventional silicon dioxide (SiO2) film is used as the interlayer insulating film and copper (Cu) having a small electrical resistivity are used as the interconnect lines respectively, in order to improve the circuit operation speed.
The multilayer interconnection, which is made of copper as a wiring material, is formed by a damascene process as described below. At first, concave portions such interconnection grooves and via holes are formed in an interlayer insulating film, and a barrier metal film is deposited in the concave portions for improving the contact property between a copper film and the interlayer insulating film and for preventing copper from being diffused. Then, after filling the concave portions with a copper film, copper interconnect lines or copper vias are formed by removing the copper film and barrier metal film exposed outside of the concave portions by CMP (chemical mechanical polishing).
For such copper interconnect lines or copper vias, the barrier metal is made for example of a TiN film, a W (tungsten) based film or the like. The electrical resistivity of the barrier metal is one, two or more orders of magnitude higher than that of copper. Because of this, there is a problem that the contribution of the barrier metal film to the formation of the interconnect lines increases as the wiring dimensions decrease, and thereby the line resistance increases.
Copper interconnection structures without using a barrier metal film have also been considered. Japanese Laid-open patent publication No. H11-40671 discloses a method of manufacturing semiconductor devices comprising a step of converting a part of a patterned insulating layer into a barrier film, a step of covering the barrier film with an adhesive layer, and a step of forming a film containing a conductive metal on the adhesive layer. The barrier film is a silicon oxynitride film which is formed by performing a plasma nitriding step on an insulating layer which is an oxide film made of a low dielectric constant material. The adhesive layer contains silicon, silicon germanium, germanium or the like. Also, the adhesive layer can contain magnesium, titanium or the like.
T. Usui et. al (“Low Resistive and Highly Reliable Cu Dual-Damascene Interconnect Technology Using Self-Formed MnSixOy Barrier Layer”; Proceedings of the IEEE 2005 International Interconnect Technology Conference (IEEE Cat. No. 05TH8780C); IEEE, Piscataway, N.J., USA, 2005, 242 Pages; 6-8 June 2005; Page 188-90) discloses the technique of forming a Cu—Mn film in a concave portion of an insulating film made of TEOS—SiO2, and using this film as a seed film, forming copper by plating. After forming a copper film, an MnSixOy barrier layer is formed by annealing to have the Cu—Mn film react with TEOS—SiO2.